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19-2879; Rev 0; 7/03
KIT ATION EVALU E AILABL AV
Dual, 10-Bit, 300Msps, Current-Output DAC with 4x/2x/1x Interpolation Filters
General Description
The MAX5858 dual, 10-bit, 300Msps digital-to-analog converter (DAC) provides superior dynamic performance in wideband communication systems. The MAX5858 integrates two 10-bit DAC cores, 2x/4x programmable digital interpolation filters, and a 1.24V reference. The MAX5858 supports single-ended and differential modes of operation. The MAX5858 dynamic performance is maintained over the entire power-supply operating range of 2.7V to 3.3V. The analog outputs support a compliance voltage of -1.0V to +1.25V. The 4x/2x programmable interpolation filters feature excellent passband distortion and noise performance. Interpolating filters minimize the design complexity of analog reconstruction filters while lowering data bus and clock speeds of the digital interface. To reduce the I/O pin count, the DAC can also operate in interleave data mode. This allows the MAX5858 to be updated on a single 10-bit bus. The MAX5858 features digital control of channel gain matching to within 0.4dB in 16 0.05dB steps. Channel matching improves sideband suppression in analog quadrature modulation applications. The on-chip 1.24V bandgap reference includes a control amplifier that allows external full-scale adjustments of both channels through a single resistor. The internal reference can be disabled and an external reference may be applied for high-accuracy applications. The MAX5858 features full-scale current outputs of 2mA to 20mA and operates from a 2.7V to 3.3V single supply. The DAC supports three modes of power-control operation: normal, low-power standby, and complete power-down. In power-down mode, the operating current is reduced to 1A. The MAX5858 is packaged in a 48-pin TQFP with exposed paddle (EP) for enhanced thermal dissipation and is specified for the extended (-40C to +85C) temperature range. o 10-Bit Resolution, Dual DAC o 300Msps Update Rate o Integrated 4x/2x Interpolating Filters o 2.7V to 3.3V Single Supply o Full Output Swing and Dynamic Performance at 2.7V Supply o Superior Dynamic Performance 75dBc SFDR at fOUT = 20MHz UMTS ACLR = 63dB at fOUT = 30.7MHz o Programmable Channel-Gain Matching o Integrated 1.24V Low-Noise Bandgap Reference o Single-Resistor Gain Control o Interleave Data Mode o Differential Clock Input Modes o EV Kit Available--MAX5858 EV Kit
Features
MAX5858
Ordering Information
PART MAX5858ECM *EP = Exposed paddle. TEMP RANGE -40C to +85C PIN-PACKAGE 48 TQFP-EP*
Pin Configuration
48 47 46 45 44 43 42 41 40 39 38 37
OUTNA
OUTPB
OUTNB
REFR
N.C.
DGND
OUTPA
DVDD
AGND
1 DA9/PD 2 DA8/DACEN 3 DA7/F2EN 4 DA6/F1EN 5 DA5/G3
AVDD
AVDD
N.C. REFO 36
REN 35 I.C. 34 CGND 33 CVDD 32 CLKXN 31 CLKXP 30 CGND 29 I.C. 28 CW 27 DB0 26 24
Applications
Communications SatCom, LMDS, MMDS, HFC, DSL, WLAN, Point-to-Point Microwave Links Wireless Base Stations Direct Digital Synthesis Instrumentation/ATE
6 DGND 7 DVDD 8 DA4/G2 9 DA3/G1 10 DA2/G0 11 DA1
MAX5858
DGND
DVDD
DB8
DB7
CLK
DB4
DB3
23
DB6
DB9
DB5
13
14
15
16
17
18
19
20
21
22
TQFP-EP
NOTE: EXPOSED PADDLE CONNECTED TO GND.
________________________________________________________________ Maxim Integrated Products
DB2
12 DA0
DB1 25
IDE
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Dual, 10-Bit, 300Msps, Current-Output DAC with 4x/2x/1x Interpolation Filters MAX5858
ABSOLUTE MAXIMUM RATINGS
AVDD, DVDD, CVDD to AGND, DGND, CGND .........-0.3V to +4V DA9-DA0, DB9-DB0, CW, REN to AGND, DGND, CGND .......................................................-0.3V to +4V IDE to AGND, DGND, CGND...................-0.3V to (DVDD + 0.3V) CLKXN, CLKXP to CGND.........................................-0.3V to +4V OUTP_, OUTN_ to AGND.......................-1.25V to (AVDD + 0.3V) CLK to DGND ..........................................-0.3V to (DVDD + 0.3V) REFR, REFO to AGND .............................-0.3V to (AVDD + 0.3V) AGND to DGND, DGND to CGND, AGND to CGND..................................................-0.3V to +0.3V Maximum Current into Any Pin (excluding power supplies) ............................................50mA Continuous Power Dissipation (TA = +70C) 48-Pin TQFP-EP (derate 36.2mW/C above +70C) ....2.898W Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Junction Temperature ......................................................+150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 165Msps, no interpolation, external reference, VREF = 1.2V, IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA > +25C guaranteed by production test. TA < +25C guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER STATIC PERFORMANCE Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error (See Gain Error Parameter Definitions Section) DYNAMIC PERFORMANCE Maximum Output DAC Update Rate Glitch Impulse fOUT = 5MHz, TA +25C fDAC = 165Msps Spurious-Free Dynamic Range to Input Update Rate Nyquist SFDR fDAC = 300Msps, 2x interpolation fOUT = 20MHz fOUT = 40MHz fOUT = 60MHz fOUT = 5MHz fOUT = 40MHz fOUT = 60MHz Spurious-Free Dynamic Range Within a Window fDAC = 200Msps, 2x interpolation; fOUT = 40MHz, span = 20MHz fDAC = 165Msps, fOUT = 5MHz, span = 4MHz MTPR ACLR fDAC = 165Msps, fOUT = 20MHz fDAC =122.88Msps, fOUT = 30.72MHz 78 69 fDAC 300 5 76 75 65 63 76 78 70 85 dBc 85 76 63 dBc dB dBc Msps pV-s INL DNL VOS GE Internal reference (Note 1) External reference RL = 0 Guaranteed monotonic, RL = 0 10 -1.25 -0.75 -0.5 -9 -5 0.5 0.25 0.1 1.5 1.5 +1.25 +0.75 +0.5 +10 +7 Bits LSB LSB LSB % SYMBOL CONDITIONS MIN TYP MAX UNITS
SFDR
Multitone Power Ratio, 8 Tones, 300kHz Spacing Adjacent Channel Leakage Ratio with UMTS
2
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Dual, 10-Bit, 300Msps, Current-Output DAC with 4x/2x/1x Interpolation Filters
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 165Msps, no interpolation, external reference, VREF = 1.2V, IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA > +25C guaranteed by production test. TA < +25C guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER Total Harmonic Distortion to Nyquist Noise Spectral Density Output Channel-to-Channel Isolation Gain Mismatch Between Channels Phase Mismatch Between Channels Wideband Output Noise ANALOG OUTPUT Full-Scale Output Current Range Output Voltage Compliance Range Output Leakage Current REFERENCE Reference Output Voltage Output-Voltage Temperature Drift Reference Output Drive Capability Reference Input Voltage Range Reference Supply Rejection Current Gain IFS/IREF -0.005dB Passband Width fOUT/ 0.5fDAC -0.01dB -0.1dB -3dB 0.604fDAC / 2 to 1.396fDAC / 2 Stopband Rejection 0.600fDAC / 2 to 1.400fDAC / 2 0.594fDAC / 2 to 1.406fDAC / 2 0.532fDAC / 2 to 1.468fDAC / 2 Group Delay INTERPOLATION FILTER (2x interpolation) 0.398 0.402 0.419 0.478 74 62 53 14 18 Data clock cycles Data clock cycles dB MHz/ MHz REN = AVDD 0.10 0.2 32 VREF0 TCVREF REN = AGND 1.14 1.24 50 50 1.25 1.32 V ppm/C A V mV/V mA/mA Power-down or standby mode IFS 2 -1.00 -5 20 +1.25 +5 mA V A SYMBOL THD ND CONDITIONS fDAC = 165Msps; fOUT = 5MHz fDAC = 165Msps; fOUT = 5MHz fOUT = 5MHz fOUT = 5MHz fOUT = 5MHz MIN TYP -72 -143 80 0.05 0.15 50 MAX UNITS dB dBm/Hz dB dB Degrees pA/Hz
MAX5858
Impulse Response Duration
22
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3
Dual, 10-Bit, 300Msps, Current-Output DAC with 4x/2x/1x Interpolation Filters MAX5858
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 165Msps, no interpolation, external reference, VREF = 1.2V, IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA > +25C guaranteed by production test. TA < +25C guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER SYMBOL -0.005dB Passband Width fOUT/ 0.5fDAC -0.01dB -0.1dB -3dB 0.302fDAC / 2 to 1.698fDAC / 2 Stopband Rejection 0.300fDAC / 2 to 1.700fDAC / 2 0.297fDAC / 2 to 1.703 fDAC / 2 0.266fDAC / 2 to 1.734fDAC / 2 Group Delay CONDITIONS MIN TYP 0.200 0.201 0.210 0.239 74 63 53 14 22 Data clock cycles Data clock cycles V 0.8 VIH = 2V VIL = 0.8V -1 -1 3 0.9 x DVDD 0.1 x DVDD CVDD / 2 0.5 Single-ended clock drive No interpolation Input Data Rate Output Settling Time Output Rise Time Output Fall Time fDATA ts 2x interpolation 4x interpolation To 0.1% error band (Note 2) 10% to 90% (Note 2) 90% to 10% (Note 2) 11 2.5 2.5 5 165 150 75 ns ns ns Msps +1 +1 V A A pF dB MHz/ MHz MAX UNITS
INTERPOLATION FILTER (4x interpolation)
Impulse Response Duration LOGIC INPUTS (IDE, CW, REN, DA9-DA0, DB9-DB0) Digital Input-Voltage High Digital Input-Voltage Low Digital Input-Current High Digital Input-Current Low Digital Input Capacitance DIGITAL OUTPUTS (CLK) Digital Output-Voltage High Digital Output-Voltage Low VOH VOL ISOURCE = 0.5mA, Figure 1 ISINK = 0.5mA, Figure 1 VIH VIL IH IIL CIN 2
27
V V
DIFFERENTIAL CLOCK INPUT (CLKXP, CLKXN) Clock Input Internal Bias Differential Clock Input Swing Clock Input Impedance TIMING CHARACTERISTICS V VP-P k
4
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Dual, 10-Bit, 300Msps, Current-Output DAC with 4x/2x/1x Interpolation Filters
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 165Msps, no interpolation, external reference, VREF = 1.2V, IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA > +25C guaranteed by production test. TA < +25C guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER DATA-to-CLK Rise Setup Time DATA-to-CLK Rise Hold Time DATA-to-CLK Fall Setup Time DATA-to-CLK Fall Hold Time Control Word to CW Fall Setup Time Control Word to CW Fall Hold Time CW High Time CW Low Time DACEN Rise-to-VOUT Stable PD Fall-to-VOUT Stable Clock Frequency at CLKXP/CLKXN Input CLKXP/CLKXN Differential Clock Input to CLK Output Delay Minimum CLKXP/CLKXN Clock High Time Minimum CLKXP/CLKXN Clock Low Time POWER REQUIREMENTS Analog Power-Supply Voltage Analog Supply Current Digital Power-Supply Voltage AVDD IAVDD DVDD (Note 4) 2.7 2.7 45 3.3 49 3.3 V mA V tSTB tPDSTB fDAC tCXD tCXH tCXL External reference Differential clock 4.6 1.5 1.5 SYMBOL tDCSR tDCHR tDCSF tDCHF tCWS tCWH (Note 3) (Note 3) (Note 3) (Note 3) CONDITIONS MIN 1.5 0.4 1.7 1.1 2.5 2.5 5 5 0.7 0.5 300 TYP MAX UNITS ns ns ns ns ns ns ns ns s ms MHz ns ns ns
MAX5858
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5
Dual, 10-Bit, 300Msps, Current-Output DAC with 4x/2x/1x Interpolation Filters MAX5858
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 165Msps, no interpolation, external reference, VREF = 1.2V, IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA > +25C guaranteed by production test. TA < +25C guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER SYMBOL CONDITIONS No interpolation fDAC = 60Msps 2x interpolation 4x interpolation Digital Supply Current (Note 4) IDVDD No interpolation fDAC = 165Msps 2x interpolation 4x interpolation fDAC = 200Msps Clock Power-Supply Voltage CVDD fDAC = 60Msps Clock Supply Current (Note 4) ICVDD fDAC = 165Msps fDAC = 200Msps, 2x interpolation or 4x interpolation (Note 5) (Note 5) No interpolation fDAC = 60Msps 2x interpolation 4x interpolation Total Power Dissipation PTOT No interpolation fDAC = 165Msps 2x interpolation 4x interpolation fDAC = 200Msps 2x interpolation 4x interpolation 2x interpolation 4x interpolation 2.7 25 69 80 4.4 1 312 435 426 504 780 762 891 870 570 mW 80 94 4.8 mA A mA MIN TYP 34 75 72 54 146 140 172 165 186 178 3.3 V 61 mA MAX UNITS
Standby Current Power-Down Current
ISTANDBY IPD
Note 1: Note 2: Note 3: Note 4: Note 5:
Including the internal reference voltage tolerance. Measured single ended with 50 load and complementary output connected to ground. Guaranteed by design, not production tested. fOUT = 5MHz. All digital inputs at 0 or DVDD. Clock signal disabled.
0.5mA
TO OUTPUT PIN 5pF
1.6V
0.5mA
Figure 1. Load Test Circuit for CLK Outputs 6 _______________________________________________________________________________________
Dual, 10-Bit, 300Msps, Current-Output DAC with 4x/2x/1x Interpolation Filters
Typical Operating Characteristics
(AVDD = DVDD = CVDD = 3V 10%, AGND = DGND = CGND = 0, external reference = 1.2V, no interpolation, IFS = 20mA, differential output, TA = +25C, unless otherwise noted.)
MAX5858
INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE
MAX5858 toc01
DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE
MAX5858 toc02
POWER DISSIPATION vs. SAMPLING RATE
fOUT = 5MHz
MAX5858 toc03
0.5 0.4 0.3 0.2 INL (LSB)
0.30 0.20 0.10 INL (LSB) 0
550 500 POWER DISSIPATION (mW) 450 400 350 300 250
0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 150 300 450 600 750 DIGITAL INPUT CODE RL = 0 900 1050
NO INTERPOLATION
-0.10 -0.20 -0.30 0 150 300 450 600 750 DIGITAL INPUT CODE RL = 0 900 1050
200 0 34 68 102 136 170 SAMPLING RATE (MHz)
POWER DISSIPATION vs. SAMPLING RATE
MAX5858 toc04
POWER DISSIPATION vs. SUPPLY VOLTAGE
MAX5858 toc05
INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE
1.27 1.26 1.25 1.24 1.23 1.22 1.21 1.20 3.3 2.7 2.8 2.9 3.0 3.1 3.2 3.3 SUPPLY VOLTAGE (V)
MAX5858 toc06
1200 1000
fOUT = 5MHz
1200 4x INTERPOLATION fCLK = 200MHz fOUT = 5MHz
1.28 INTERNAL REFERENCE VOLTAGE (V)
POWER DISSIPATION (mW)
1000 POWER DISSIPATION (mW)
2x INTERPOLATION 800 4x INTERPOLATION 600
800 2x INTERPOLATION fCLK = 200MHz fOUT = 5MHz
600
400
400
200 0 50 100 150 200 250 300 SAMPLING RATE (MHz)
200 2.7 2.8 2.9 3.0
NO INTERPOLATION fCLK = 165MHz fOUT = 5MHz 3.1 3.2
SUPPLY VOLTAGE (V)
INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE
1.27 1.26 1.25 1.24 1.23 1.22 1.21 1.20 -40 -15 10 35 60 85
MAX5858 toc07
DYNAMIC RESPONSE RISE TIME
MAX5858 toc08
DYNAMIC RESPONSE FALL TIME
MAX5858 toc09
1.28 INTERNAL REFERENCE VOLTAGE (V)
200mV/div
200mV/div
RL = 50 SINGLE ENDED 10ns/div
RL = 50 SINGLE ENDED 10ns/div
TEMPERATURE (C)
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7
Dual, 10-Bit, 300Msps, Current-Output DAC with 4x/2x/1x Interpolation Filters MAX5858
Typical Operating Characteristics (continued)
(AVDD = DVDD = CVDD = 3V 10%, AGND = DGND = CGND = 0, external reference = 1.2V, no interpolation, IFS = 20mA, differential output, TA = +25C, unless otherwise noted.)
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (NO INTERPOLATION, fDAC = 165MHz)
MAX5858 toc10
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (NO INTERPOLATION, fDAC = 65MHz)
MAX5858 toc11
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (2x INTERPOLATION, fDAC = 300MHz)
90 80 70 SFDR (dBc) AOUT = 0dB FS
MAX5858 toc12
100 90 80 70 SFDR (dBc) AOUT = 0dB FS AOUT = -6dB FS
100 90 80 70 SFDR (dBc) 60 50 40 30 20 10 0 AOUT = -6dB FS AOUT = -12dB FS AOUT = 0dB FS
100
60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 90 OUTPUT FREQUENCY (MHz) AOUT = -12dB FS
60 50 40 30 20 10 0 AOUT = -12dB FS AOUT = -6dB FS
0
5
10
15
20
25
30
35
0
10
20
30
40
50
60
70
80
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (2x INTERPOLATION, fDAC = 165MHz)
MAX5858 toc13
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (4x INTERPOLATION, fDAC = 300MHz)
MAX5858 toc14
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (4x INTERPOLATION, fDAC = 165MHz)
90 80 70 AOUT = 0dB FS
MAX5858 toc15
100 90 80 70 SFDR (dBc) AOUT = -6dB FS
100 90 80 70 SFDR (dBc) AOUT = -6dB FS
100
50 40 30 20 10 0 0
AOUT = 0dB FS AOUT = -12dB FS
50 40 30 20 10 0
AOUT = -12dB FS
AOUT = 0dB FS
SFDR (dBc)
60
60
60 50 40 30 20 10 0
AOUT = -6dB FS AOUT = -12dB FS
5
10
15
20
25
30
35
40
45
0
5
10
15
20
25
30
35
40
0
3
6
9
12
15
18
21
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
8
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Dual, 10-Bit, 300Msps, Current-Output DAC with 4x/2x/1x Interpolation Filters
Typical Operating Characteristics (continued)
(AVDD = DVDD = CVDD = 3V 10%, AGND = DGND = CGND = 0, external reference = 1.2V, no interpolation, IFS = 20mA, differential output, TA = +25C, unless otherwise noted.)
MAX5858
SPURIOUS-FREE DYNAMIC RANGE vs. TEMPERATURE (NO INTERPOLATION, fDAC = 165MHz, fOUT = 5MHz)
MAX5858 toc16
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (NO INTERPOLATION, fDAC = 165MHz)
MAX5858 toc17
FFT PLOT (2MHz WINDOW)
-10 -20 OUTPUT POWER (dBm) -30 -40 -50 -60 -70 -80 -90 fDAC = 165MHz fOUT = 9.7MHz AOUT = -6dB FS
MAX5858 toc18
100 90 80 70 SFDR (dBc) AOUT = -6dB FS AOUT = 0dB FS AOUT = -12dB FS
100 90 80 70 SFDR (dBc) 60 50 40 30 20 10 0 AOUT = 0dB FS 0 10 20 30 40 50 60 70 80 TA = +85C TA = -10C TA = +25C
0
60 50 40 30 20 10 0 -40 -15 -10 35 60 85 TEMPERATURE (C)
-100 90 7.7 8.2 8.7 9.2 9.7 10.2 10.7 11.2 11.7 OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
FFT PLOT FOR NYQUIST WINDOW (NO INTERPOLATION, fDAC = 165MHz, fOUT = 10MHz, AOUT = 0dB FS)
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -119 0 8.25 16.50 33.00 66.00 82.50 49.50 24.75 41.25 57.75 74.25 OUTPUT FREQUENCY (MHz)
MAX5858 toc19
FFT PLOT FOR DAC UPDATE NYQUIST WINDOW (100MHz) (2x INTERPOLATION, fDAC = 200MHz, fOUT = 10MHz, AOUT = 0dB FS)
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -119 0 10 20 30 40 50 60 70 80 90 100 OUTPUT FREQUENCY (MHz)
MAX5858 toc20
FFT PLOT FOR DAC UPDATE NYQUIST WINDOW (100MHz) (4x INTERPOLATION, fDAC = 200MHz, fOUT = 10MHz, AOUT = 0dB FS)
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -119 0 10 20 30 40 50 60 70 80 90 100 OUTPUT FREQUENCY (MHz)
MAX5858 toc21
OUTPUT POWER (dBm)
OUTPUT POWER (dBm)
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OUTPUT POWER (dBm)
9
Dual, 10-Bit, 300Msps, Current-Output DAC with 4x/2x/1x Interpolation Filters MAX5858
Typical Operating Characteristics (continued)
(AVDD = DVDD = CVDD = 3V 10%, AGND = DGND = CGND = 0, external reference = 1.2V, no interpolation, IFS = 20mA, differential output, TA = +25C, unless otherwise noted.)
2-TONE IMD PLOT (NO INTERPOLATION, fDAC = 165MHz)
MAX5858 toc22
8-TONE MTPR PLOT (NO INTERPOLATION, fDAC = 165MHz, fCENTER = 19.9503MHz)
-10 -20 OUTPUT POWER (dBm) -30 -40 -50 -60 -70 -80 -90 fT3 fT8 fT1 fT2 fT4 fT5 fT6 fT7
AOUT = 18dB FS BW = 3MHz
MAX5858 toc23
8-TONE MTPR PLOT (4x INTERPOLATION, fDAC = 286.4MHz, fCENTER = 29.9572MHz)
-10 -20 OUTPUT POWER (dBm) -30 -40 -50 -60 -70 -80 -90 fT3 fT1 fT4 fT2 fT5 fT7 fT8 fT6
AOUT = 18dB FS BW = 3MHz
MAX5858 toc24
0 -10 -20 OUTPUT POWER (dBm) -30 -40 -50 -60 -70 -80 -90 -100
AOUT = -6dB FS BW = 1MHz fT1
fT1 = 4.9448MHz fT2 = 5.0656MHz fT2
0
0
2 x fT1 - fT2
2 x fT2 - fT1
4.5
4.7 4.9 5.1 5.3 OUTPUT FREQUENCY (MHz)
5.5
-100 18.5
19.0
19.5 20.0 20.5 21.0 OUTPUT FREQUENCY (MHz)
fT5 = 20.2524MHz fT6 = 20.5344MHz fT7 = 20.8365MHz fT8 = 21.1386MHz
21.5
-100 28.5
29.0
29.5 30.0 30.5 31.0 OUTPUT FREQUENCY (MHz)
fT5 = 30.2281MHz fT6 = 30.5952MHz fT7 = 30.8924MHz fT8 = 31.1546MHz
31.5
fT1 = 18.8022MHz fT2 = 19.0237MHz fT3 = 19.2654MHz fT4 = 19.6481MHz
fT1 = 28.7597MHz fT2 = 29.1008MHz fT3 = 29.3628MHz fT4 = 29.6862MHz
8-TONE MTPR PLOT FOR NYQUIST WINDOW (NO INTERPOLATION, fDAC = 165MHz, fCENTER = 19.9569MHz, AOUT = -18dB FS)
MTPR = 76dBc
MAX5858 toc25
8-TONE MTPR PLOT FOR DAC UPDATE (WITHIN A NYQUIST WINDOW) (x4 INTERPOLATION, fDAC = 286.4MHz, fCENTER = 20MHz, INPUT TONES SPACED 300kHz APART,AOUT = -18dB FS)
-20 -30 OUTPUT POWER (dBm) -40 -50 -60 -70 -80 -90 -100 -110 A B
MAX5858 toc26
ACLR UMTS PLOT (NO INTERPOLATION, fDAC = 122.88MHz, fDATA = 122.88MHz, fCENTER = 30.72MHz)
ACLR = 63dB
MAX5858 toc27
-1 -10 -20 OUTPUT POWER (dBm) -30 -40 -50 -60 -70 -80 -90
-10 35.8MHz
-25 -30 -40 -50 OUTPUT POWER (dB) -60 -70 -80 -90 -100 -110 -120 -125
A: IN-BAND-RANGE B: OUT-OF-BAND RANGE
-100 1.00
17.30 33.60 66.20 82.50 49.90 9.15 25.25 41.75 58.05 74.35 OUTPUT FREQUENCY (MHz)
1.0 15.2
28.6 42.9
57.2 71.5
85.8
114.4 143.2 100.1 128.7
0
6.14MHz/div OUTPUT FREQUENCY (MHz)
61.44
OUTPUT FREQUENCY (MHz)
10
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Dual, 10-Bit, 300Msps, Current-Output DAC with 4x/2x/1x Interpolation Filters
Typical Operating Characteristics (continued)
(AVDD = DVDD = CVDD = 3V 10%, AGND = DGND = CGND = 0, external reference = 1.2V, no interpolation, IFS = 20mA, differential output, TA = +25C, unless otherwise noted.)
MAX5858
ACLR WITH UMTS PLOT (NO INTERPOLATION, fDAC = 122.88MHz, fDATA = 122.88MHz, fCENTER = 30.72MHz)
MAX5858 toc28
ACLR WITH UMTS PLOT (2x INTERPOLATION, fDAC = 245.76MHz, fDATA = 122.88MHz, fCENTER = 30.72MHz)
MAX5858 toc29
ACLR WITH UMTS PLOT (2x INTERPOLATION, fDAC = 245.76MHz, fDATA = 122.88MHz, fCENTER = 30.72MHz)
ACLR = 63dB
MAX5858 toc30
-25 -30 -40 -50 OUTPUT POWER (dB)
ACLR = 63dB
-25 -30 -40 -50 OUTPUT POWER (dB) -60 -70 -80 -90 -100 -110 -120 -125 ACLR = 63dB
-25 -30 -40 -50 OUTPUT POWER (dB) -60 -70 -80 -90 -100 -110 -120 -125
-60 -70 -80 -90 -100 -110 -120 -125 0
12.288MHz/div OUTPUT FREQUENCY (MHz)
122.88
0
6.14MHz/div OUTPUT FREQUENCY (MHz)
61.44
0
12.288MHz/div OUTPUT FREQUENCY (MHz)
122.88
Pin Description
PIN 1 NAME DA9/PD FUNCTION Channel A Input Data Bit 9 (MSB)/Power-Down Control Bit: 0: Enter DAC standby mode (DACEN = 0) or power up DAC (DACEN = 1). 1: Enter power-down mode.
2
Channel A Input Data Bit 8/DAC Enable Control Bit: 0: Enter DAC standby mode with PD = 0. DA8/DACEN 1: Power up DAC with PD = 0. X: Enter power-down mode with PD = 1 (X = don't care). DA7/F2EN Channel A Input Data Bit 7/Second Interpolation Filter Enable Bit: 0: Interpolation mode is determined by F1EN. Enable 4x interpolation mode. (F1EN must equal 1.) Channel A Input Data Bit 6/First Interpolation Filter Enable Bit: 0: Interpolation disable. 1: Enable 2x interpolation. Channel A Input Data Bit 5/Channel A Gain Adjustment Bit 3 Digital Ground Digital Power Supply. See the Power Supplies, Bypassing, Decoupling, and Layout section. Channel A Input Data Bit 4/Channel A Gain Adjustment Bit 2 Channel A Input Data Bit 3/Channel A Gain Adjustment Bit 1
3
4 5 6, 19, 47 7, 18, 48 8 9
DA6/F1EN DA5/G3 DGND DVDD DA4/G2 DA3/G1
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11
Dual, 10-Bit, 300Msps, Current-Output DAC with 4x/2x/1x Interpolation Filters MAX5858
Pin Description (continued)
PIN 10 11 12 13 14 15 16 17 20 21 22 23 24 25 26 27 28, 34 29, 33 30 31 32 35 36 37, 38 39 40, 46 41 42 43 44 45 -- NAME DA2/G0 DA1 DA0 DB9 DB8 DB7 DB6 DB5 CLK IDE DB4 DB3 DB2 DB1 DB0 CW I.C. CGND CLKXP CLKXN CVDD REN REFO N.C. REFR AVDD OUTNB OUTPB AGND OUTNA OUTPA EP Channel A Input Data Bit 1 Channel A Input Data Bit 0 (LSB) Channel B Input Data Bit 9 (MSB) Channel B Input Data Bit 8 Channel B Input Data Bit 7 Channel B Input Data Bit 6 Channel B Input Data Bit 5 Clock Output Interleave Data Mode Enable. When IDE is high, data for both DAC channels is written through port A (bits DA9-DA0). When IDE is low, channel A data is latched on the rising edge of CLK and channel B is latched on the falling edge of CLK. Channel B Input Data Bit 4 Channel B Input Data Bit 3 Channel B Input Data Bit 2 Channel B Input Data Bit 1 Channel B Input Data Bit 0 (LSB) Active-Low Control Word Write Pulse. The control word is latched on the falling edge of CW. Internally Connected. Do not connect. Clock Ground Differential Clock Input Positive Terminal. Bypass CLKXP with a 0.01F capacitor to CGND when CLKXN is in single-ended mode. Differential Clock Input Negative Terminal. Bypass CLKXN with a 0.01F capacitor to CGND when CLKXP is in single-ended mode. Clock Power Supply. See the Power Supplies, Bypassing, Decoupling, and Layout section. Active-Low Reference Enable. Connect REN to AGND to activate the on-chip 1.24V reference. Reference I/O. REFO serves as the reference input when the internal reference is disabled. If the internal 1.24V reference is enabled, REFO serves as the output for the internal reference. When the internal reference is enabled, bypass REFO to AGND with a 0.1F capacitor. No Connection. Not internally connected. Full-Scale Current Adjustment. To set the output full-scale current, connect an external resistor RSET between REFR and AGND. The output full-scale current is equal to 32 x VREFO/RSET. Analog Power Supply. See Power Supplies, Bypassing, Decoupling, and Layout section. Channel B Negative Analog Current Output Channel B Positive Analog Current Output Analog Ground Channel A Negative Analog Current Output Channel A Positive Analog Current Output Exposed Pad. Connect to the ground plane. FUNCTION Channel A Input Data Bit 2/Channel A Gain Adjustment Bit 0
12
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Dual, 10-Bit, 300Msps, Current-Output DAC with 4x/2x/1x Interpolation Filters
Simplified Block Diagram
DVDD CVDD AVDD CLKXP CLKXN CLK
MAX5858
MAX5858
OUTPA 10 DA9-DA0 INPUT REGISTER 10 2x DIGITAL INTERPOLATION FILTER 10 2x DIGITAL INTERPOLATION FILTER 10 10-BIT 300MHz DAC OUTNA OUTPB 10 DB9-DB0 INPUT REGISTER 10 2x DIGITAL INTERPOLATION FILTER 10 2x DIGITAL INTERPOLATION FILTER 10 10-BIT 300MHz DAC OUTNB IDE F1EN F2EN
CW
CONTROL REGISTER
1.24V REFERENCE AND CONTROL AMPLIFIER
DGND
CGND
REFO
REN
REFR RSET
AGND
Detailed Description
The MAX5858 dual, high-speed, 10-bit, current-output DAC provides superior performance in communication systems requiring low-distortion analog-signal reconstruction. The MAX5858 combines two DACs with 2x/4x programmable digital interpolation filters, divide-by-N clock output, and an on-chip 1.24V reference. The current outputs of the DACs can be configured for differential or single-ended operation. The full-scale output current range is adjustable from 2mA to 20mA to optimize power dissipation and gain control. The MAX5858 accepts an input data rate to 165MHz or a DAC conversion rate of 300MHz. The inputs are latched on the rising edge of the clock whereas the output latches on the following rising edge. The two-stage digital interpolation filters are programmable to 4x, 2x, or no interpolation. When operating in 4x interpolation mode, the interpolator increases the DAC conversion by a factor of four, providing a four-
fold increase in separation between the reconstructed waveform spectrum and its first image. The MAX5858 features three modes of operation: normal, standby, and power-down. These modes allow efficient power management. In power-down, the MAX5858 consumes only 1A of supply current. Wake-up time from standby mode to normal DAC operation is 0.7s.
Programming the DAC
An 8-bit control word routed through channel A's data port programs the gain matching, interpolator configuration, and operational mode of the MAX5858. The control word is latched on the falling edge of CW. Table 1 represents the control word format and function. The gain on channel A can be adjusted to achieve gain matching between two channels in a user's system. The gain on channel A can be adjusted from -0.4dB to 0.35dB in steps of 0.05dB by using bits G3 to G0 (see Table 3).
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13
Dual, 10-Bit, 300Msps, Current-Output DAC with 4x/2x/1x Interpolation Filters MAX5858
Device Power-Up and States of Operation
At power-up, the MAX5858's default configuration is no-interpolation mode with a gain of 0dB and a fully operational converter. In shutdown, the MAX5858 consumes only 1A of supply current, and in standby the current consumption is 4.4mA. Wake-up time from standby mode to normal operation is 0.7s. The programmable interpolation filters multiply the MAX5858 input data rate by a factor of 2x or 4x to separate the reconstructed waveform spectrum and the first image. The original spectral images, appearing around multiples of the DAC input data rate, are attenuated at least 60dB by the internal digital filters. This feature provides three benefits: 1) Image separation reduces complexity of analog reconstruction filters. 2) Lower input data rates eliminate board level highspeed data transmission. 3) Sin(x)/x roll-off is reduced over the effective bandwidth. Figure 2 shows an application circuit and Figure 3 illustrates a practical example of the benefits when using the MAX5858 in 4x-interpolation mode. The example illustrates signal synthesis of a 20MHz IF with a 10MHz bandwidth. The designer can consider three options to address the design challenge. The tradeoffs for each solution are depicted in Table 4.
Interpolation Filters
The MAX5858 features a two stage, 2x digital interpolating filter based on 43-tap and 23-tap FIR topology. F1EN and F2EN enable the interpolation filters. F1EN high enables the first filter for 2x interpolation and F2EN high enables the second filter for combined 4x interpolation. To bypass and disable both interpolation filters (no-interpolation mode or 1x mode) set F1EN = F2EN = 0. When set for 1x mode the filters are powered down and consume virtually no current. An illegal condition is defined by: F1EN = 0, F2EN = 1 (see Table 2 for configuration modes).
Table 1. Control Word Format and Function
MSB PD DACEN F2EN F1EN G3 G2 FUNCTION Power-Down. The part enters power-down mode if PD = 1. DAC Enable. When DACEN = 0 and PD = 0, the part enters standby mode. Filter Enable. When F2EN = 1 and F1EN = 1, 4x interpolation is enabled. When F2EN = 0, the interpolation mode is determined by F1EN. Filter Enable. When F1EN = 1 and F2EN = 0, 2x interpolation is active. With F1EN = 0 and F2EN = 0, the interpolation is disabled. Bit 3 (MSB) of Gain Adjust Word. Bit 2 of Gain Adjust Word. Bit 1 of Gain Adjust Word. Bit 0 (LSB) of Gain Adjust Word. G1 G0 X LSB X
CONTROL WORD PD DACEN F2EN F1EN G3 G2 G1 G0
Table 2. Configuration Modes
MODE No interpolation 2x interpolation 4x interpolation Standby Power-down PD 0 0 0 0 1 0 DACEN 1 1 1 0 X 1 F2EN 0 0 1 X X X F1EN 0 1 1 X X X
Table 3. Gain Difference Setting
GAIN ADJUSTMENT ON CHANNEL A (dB) +0.4 0 -0.35 G3 0 1 1 G2 0 0 1 G1 0 0 1 G0 0 0 1
Power-up X = Don't care. F1EN = 0, F2EN = 1 illegal.
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Dual, 10-Bit, 300Msps, Current-Output DAC with 4x/2x/1x Interpolation Filters MAX5858
SINGLE SUPPLY 2.7V TO 3.3V FS ANALOG OUT MAINTAINED OVER ENTIRE SUPPLY RANGE 2.7V TO 3.3V
SINGLE 10-BIT BUS SAVES I/O PINS
DATA LATCH 10-BIT INTERLEAVE DATA LATCH DATA LATCH 10-BIT BUS
INTERPOLATING FILTERS 4x/2x
CH-1 DAC
AOUT1
DIGITAL BASEBAND OFDM PROCESSOR QAM-MAPPER
INTERPOLATING FILTERS 4x/2x
CH-2 DAC
AOUT2
DIV-4 DIV-2 DIV-1 DATA CLOCK OUT fDATA = 71.6MHz CLOCK SOURCE fDAC = 286.4MHz
Figure 2. Typical Application Circuit
Table 4. Benefits of Interpolation
OPTION 1 SOLUTION * No interpolation * 2.6x oversample * fDAC = fDATA = 78MHz * * * * * * * * No interpolation 8x oversample fDAC = fDATA = 240MHz Push image to fIMAGE = 210MHz 4x interpolation fDAC = 286.4MHz, fDATA = 71.6MHz Passband attenuation = 0.1dB Push image to 256MHz ADVANTAGE * Low data rate * Low clock rate DISADVANTAGE * High order filter * Filter gain/phase match
2
* Lower order filter * Filter gain/phase match * * * * Low data rate Low order filter 60dB image attenuate Filter gain/phase match
* High clock rate * High data rate
3
* None
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15
Dual, 10-Bit, 300Msps, Current-Output DAC with 4x/2x/1x Interpolation Filters MAX5858
SOLUTION 1 IMAGE SEPARATION = 18MHz LESS THAN ONE OCTAVE HIGH ORDER ANALOG FILTER
fOUT 20MHz 10MHz
IMAGE fDAC - fOUT 48MHz
fDAC 78MHz
IMAGE fDAC + fOUT 108MHz
FREQUENCY AXIS NOT TO SCALE
SOLUTION 2 LOWER ORDER ANALOG FILTER IMAGE SEPARATION = 180MHz HIGH-SPEED CLK = 240MHz
fOUT 20MHz BW = 10MHz FREQUENCY AXIS NOT TO SCALE SOLUTION 3 SIMPLE ANALOG FILTER
fDAC IMAGE IMAGE fDAC - fOUT 240MHz fDAC + fOUT 210MHz 270MHz
NEW FIRST IMAGE SEPARATION > 3 OCTAVES DIGITAL FILTER ATTENUATION >60dB
fOUT 20MHz BW = 10MHz
fDATA 71.6MHz FREQUENCY AXIS NOT TO SCALE
fDAC IMAGE IMAGE fDAC - fOUT 286MHz fDAC + fOUT 256MHz 316MHz
Figure 3. MAX5858 in 4x Interpolation Mode
This example demonstrates that 4x interpolation with digital filtering yields significant benefits in reducing system complexity, improving dynamic performance and lowering cost. Data can be written to the MAX5858 at much lower speeds while achieving image attenuation greater than 60dB and image separation beyond three octaves. The main benefit is in analog reconstruc16
tion filter design. Reducing the filter order eases gain/phase matching while lowering filter cost and saving board space. Because the data rate is lowered to 71.6MHz, the setup and hold times are manageable and the clock signal source is simplified, which results in improved system reliability and lower cost.
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Dual, 10-Bit, 300Msps, Current-Output DAC with 4x/2x/1x Interpolation Filters MAX5858
OPTIONAL EXTERNAL BUFFER FOR HEAVIER LOADS REN MAX4040 1.24V BANDGAP REFERENCE REFO CCOMP* REFR AGND IREF = VREF RSET AGND *COMPENSATION CAPACITOR (CCOMP 100nF). RSET CURRENTSOURCE ARRAY IFS AGND
IREF
MAX5858
Figure 4. Setting IFS with the Internal 1.24V Reference and the Control Amplifier
Clocking Modes
Apply an external clock to CLKXP and CLKXN at the desired DAC update rate and allowable input amplitude. CLK is an output and provides the signal necessary to synchronize the input data. CLKXP and CLKXN accept a frequency range of 0 to 300MHz (see Table 5). Maintain a low capacitive load at the CLK output (not higher than 10pF for fCLK of 165MHz).
RSET is the reference resistor that determines the amplifier output current of the MAX5858 (Figure 4). This current is mirrored into the current-source array where IFS is equally distributed between matched current segments and summed to valid output current readings for the DACs.
External Reference
To disable the internal reference of the MAX5858, connect REN to AVDD. Apply a temperature-stable, external reference to drive the REFO to set the full-scale output (Figure 5). For improved accuracy and drift performance, choose a fixed output voltage reference such as the 1.24V, 25ppm/C MAX6520 bandgap reference.
Internal Reference and Control Amplifier
The MAX5858 provides an integrated 50ppm/C, 1.24V, low-noise bandgap reference that can be disabled and overridden with an external reference voltage. REFO serves either as an external reference input or an integrated reference output. If REN is connected to AGND, the internal reference is selected and REFO provides a 1.24V (50A) output. Buffer REFO with an external amplifier, when driving a heavy load. The MAX5858 also employs a control amplifier designed to simultaneously regulate the full-scale output current (I FS ) for both outputs of the devices. Calculate the output current as: IFS = 32 IREF where I REF is the reference output current (I REF = VREFO/RSET) and IFS is the full-scale output current.
Detailed Timing
The MAX5858 accepts an input data rate up to 165MHz or the DAC conversion rate of 300MHz. The input latches on the rising edge of the clock, whereas the output latches on the following rising edge. Figure 6 depicts the write cycle of the DACs in 4x interpolation mode. In this timing diagram, signals applied to CLKXP and CLKXN are divided by four to create the DAC's CLK signal. The MAX5858 DAC output is updated at the rate of the clock applied to CLKXP/CLKXN.
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17
Dual, 10-Bit, 300Msps, Current-Output DAC with 4x/2x/1x Interpolation Filters MAX5858
AVDD 10F REN 1.24V BANDGAP REFERENCE REFO CURRENTSOURCE ARRAY IREF RSET IFS AGND 0.1F
AVDD
EXTERNAL +1.24V REFERENCE
REFR
MAX6520
AGND
MAX5858
AGND
Figure 5. MAX5858 with External Reference
Table 5. Clocking Modes
F2EN 0 0 1 1 F1EN 0 1 1 0 DIFFERENTIAL CLOCK FREQUENCY (fCLKDIFF) (MHz) 0 to 165 0 to 300 0 to 300 CLK OUTPUT (MHz) FCLKDIFF FCLKDIFF/2 fCLKDIFF/4 DAC RATE (fDAC) fCLKDIFF fCLKDIFF fCLKDIFF Illegal INTERPOLATION 1x 2x 4x MAX SIGNAL BANDWIDTH (MHz) 82 63 31
The MAX5858 can also operate in an interleave data mode. Pulling IDE high activates this mode. In interleave mode, data for both DAC channels is written through input port A. Channel B data is written on the falling edge of the CLK signal and then channel A data is written on the following rising edge of the CLK signal. Both DAC outputs (channel A and B) are updated simultaneously on the next following rising edge of the CLK. In interleave data mode, the maximum input data rate per channel is half of the rate in noninterleave mode. The interleave data mode is attractive in applications where lower data rates are acceptable and interfacing on a single 10-bit bus is desired (Figure 7).
Applications Information
Differential-to-Single-Ended Conversion
The MAX5858 exhibits excellent dynamic performance to synthesize a wide variety of modulation schemes, including high-order QAM modulation with OFDM. Figure 8 shows a typical application circuit with output transformers performing the required differential-to-single-ended signal conversion. In this configuration, the MAX5858 operates in differential mode, which reduces even-order harmonics, and increases the available output power.
18
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Dual, 10-Bit, 300Msps, Current-Output DAC with 4x/2x/1x Interpolation Filters MAX5858
CLKXN1 tCXD CLKXP1 tCWH tCXD
CW tCWS CLK
DA0-DA9/ CONTROL WORD
DAN
CONTROL WORD
DAN+1
DB0-DB9 tDCSR
DBN
DBN+1 tDCHR
1-THE DIAGRAM SHOWS 4x INTERPOLATION MODE.
Figure 6. Timing Diagram for Noninterleave Data Mode (IDE = Low)
CLKXN1 tCXD CLKXP1 tCXD
CLK
DA0-DA9 tDCSR
DAN
DBN+1 tDCSF tDCHF
DAN+1
DBN+2
DAN+2 tDCHR
1-THE DIAGRAM SHOWS 4x INTERPOLATION MODE.
Figure 7. Timing Diagram for Interleave Data Mode (IDE = High)
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19
Dual, 10-Bit, 300Msps, Current-Output DAC with 4x/2x/1x Interpolation Filters MAX5858
AVDD DVDD CVDD 50 OUTPA DA0-DA9 AVDD DVDD CVDD 50 OUTPA
VOUTA, SINGLE ENDED DA0-DA9
1/2
100
1/2 MAX5858
OUTNA 50
10
MAX5858
OUTNA 50
10
50 OUTPB DB0-DB9
VOUTB, SINGLE ENDED DB0-DB9
50 OUTPB
1/2
100
1/2 MAX5858
OUTNB
10
MAX5858
OUTNB 50 AGND DGND CGND
10
50
AGND DGND CGND
Figure 8. Application with Output Transformer Performing Differential to Single-Ended Conversion
Figure 9. Application with DC-Coupled Differential Outputs
Differential DC-Coupled Configuration
Figure 9 shows the MAX5858 output operating in differential, DC-coupled mode. This configuration can be used in communication systems employing analog quadrature upconverters and requiring a baseband sampling, dual-channel, high-speed DAC for I/Q synthesis. In these applications, information bandwidth can extend from 10MHz down to several hundred kilohertz. DC-coupling is desirable in order to eliminate long discharge time constants that are problematic with large, expensive coupling capacitors. Analog quadrature upconverters have a DC common-mode input requirement of typically 0.7V to 1.0V. The MAX5858 differential I/Q outputs can maintain the desired full-scale frequency spectrum at the required 0.7V to 1.0V DC commonmode level when powered from a single 2.85V (5%) supply. The MAX5858 meets this low-power requirement with minimal reduction in dynamic range while eliminating the need for level-shifting resistor networks.
Power Supplies, Bypassing, Decoupling, and Layout
Grounding and power-supply decoupling strongly influence the MAX5858 performance. Unwanted digital crosstalk can couple through the input, reference, power-supply, and ground connections, which can affect dynamic specifications, like signal-to-noise ratio or spurious-free dynamic range. In addition, electromagnetic interference (EMI) can either couple into or be generated by the MAX5858. Observe the grounding and power-supply decoupling guidelines for highspeed, high-frequency applications. Follow the power supply and filter configuration to realize optimum dynamic performance. Use of a multilayer printed circuit (PC) board with separate ground and power-supply planes is recommended. Run high-speed signals on lines directly above the ground plane. The MAX5858 has separate analog and digital ground buses (AGND, CGND, and DGND,
20
______________________________________________________________________________________
Dual, 10-Bit, 300Msps, Current-Output DAC with 4x/2x/1x Interpolation Filters
respectively). Provide separate analog, digital, and clock ground sections on the PC board with only one point connecting the three planes. The ground connection points should be located underneath the device and connected to the exposed paddle. Run digital signals above the digital ground plane and analog/clock signals above the analog/clock ground plane. Digital signals should be kept away from sensitive analog, clock, and reference inputs. Keep digital signal paths short and metal trace lengths matched to avoid propagation delay and data skew mismatch. The MAX5858 includes three separate power-supply inputs: analog (AV DD ), digital (DV DD ), and clock (CVDD). Use a single linear regulator power source to branch out to three separate power-supply lines (AVDD, DV DD , CV DD ) and returns (AGND, DGND, CGND). Filter each power-supply line to the respective return line using LC filters comprising ferrite beads and 10F capacitors. Filter each supply input locally with 0.1F ceramic capacitors to the respective return lines. Note: To maintain the dynamic performance of the Electrical Characteristics, ensure the voltage difference between DV DD , AV DD , and CV DD does not exceed 150mV. implementing large ground planes in the PC board design will allow for highest performance operation of the DAC. Use an array of 3 3 (or greater) vias (0.3mm diameter per via hole and 1.2mm pitch between via holes) for this 48-pin TQFP-EP package.
MAX5858
Dynamic Performance Parameter Definitions
Adjacent Channel Leakage Ratio (ACLR) Commonly used in combination with wideband codedivision multiple-access (WCDMA), ACLR reflects the leakage power ratio in dB between the measured power within a channel relative to its adjacent channel. ACLR provides a quantifiable method of determining out-of-band spectral energy and its influence on an adjacent channel when a bandwidth-limited RF signal passes through a nonlinear device. Total Harmonic Distortion (THD) THD is the ratio of the RMS sum of all essential harmonics (within a Nyquist window) of the input signal to the fundamental itself. This can be expressed as: THD = 20 x log
Thermal Characteristics and Packaging
Thermal Resistance 48-lead TQFP-EP: JA = 37C/W Keep the device junction temperature below +125C to meet specified electrical performance. Lower the power-supply voltage to maintain specified performance when the DAC update rate approaches 300Msps and the ambient temperature equals +85C. The MAX5858 is packaged in a 48-pin TQFP-EP package, providing greater design flexibility, increased thermal efficiency, and optimized AC performance of the DAC. The EP enables the implementation of grounding techniques, which are necessary to ensure highest performance operation. In this package, the data converter die is attached to an EP leadframe with the back of this frame exposed at the package bottom surface, facing the PC board side of the package. This allows a solid attachment of the package to the PC board with standard infrared (IR)flow soldering techniques. A specially created land pattern on the PC board, matching the size of the EP (5mm 5mm), ensures the proper attachment and grounding of the DAC. Designing vias* into the land area and
*Vias connect the land pattern to internal or external copper planes.
(V2
2
+ V32 + V42... + ...VN2 / V1
)
where V1 is the fundamental amplitude, and V2 through VN are the amplitudes of the 2nd through Nth order harmonics. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio of RMS amplitude of the carrier frequency (maximum signal component) to the RMS value of their next-largest spectral component. SFDR is usually measured in dBc with respect to the carrier frequency amplitude or in dB FS with respect to the DAC's full-scale range. Depending on its test condition, SFDR is observed within a predefined window or to Nyquist. Multitone Power Ratio (MTPR) A series of equally spaced tones are applied to the DAC with one tone removed from the center of the range. MTPR is defined as the worst-case distortion (usually a 3rd-order harmonic product of the fundamental frequencies), which appears as the largest spur at the frequency of the missing tone in the sequence. This test can be performed with any number of input tones; however, four and eight tones are among the most common test conditions for CDMA- and GSM/EDGE-type applications.
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21
Dual, 10-Bit, 300Msps, Current-Output DAC with 4x/2x/1x Interpolation Filters MAX5858
Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in dBc of either output tone to the worst 3rd-order (or higher) IMD products. Gain Error A gain error is the difference between the ideal and the actual full-scale output current on the transfer curve, after nullifying the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step. The ideal current is defined by reference voltage at VREFO / IREF x 32. Settling Time The settling time is the amount of time required from the start of a transition until the DAC output settles to its new output value to within the converter's specified accuracy. Glitch Impulse A glitch is generated when a DAC switches between two codes. The largest glitch is usually generated around the midscale transition, when the input pattern transitions from 011...111 to 100...000. This occurs due to timing variations between the bits. The glitch impulse is found by integrating the voltage of the glitch at the midscale transition over time. The glitch impulse is usually specified in pV-s.
Static Performance Parameter Definitions
Integral Nonlinearity (INL) Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. For a DAC, the deviations are measured at every individual step. Differential Nonlinearity (DNL) Differential nonlinearity (DNL) is the difference between an actual step height and the ideal value of 1 LSB. A DNL error specification no more negative than -1 LSB guarantees monotonic transfer function.
Offset Error
Offset error is the current flowing from positive DAC output when the digital input code is set to zero. Offset error is expressed in LSBs.
Chip Information
TRANSISTOR COUNT: 178,376 PROCESS: CMOS
22
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Dual, 10-Bit, 300Msps, Current-Output DAC with 4x/2x/1x Interpolation Filters
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
48L,TQFP.EPS
MAX5858
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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